1. Field of the Invention
The present invention relates to semiconductor integrated circuits, particularly to a circuit configuration of a voltage down converter.
2. Description of the Background Art
Reflecting the demand for multifunction circuitry and lower power consumption, attention is now focused on a circuit that has ASIC (Application Specific IC) circuitry and DRAM (Dynamic Random Access Memory) circuitry embedded in one chip (referred to as an eDRAM (embedded Dynamic Random Access Memory) circuit hereinafter).
Also, there is a demand for miniaturization of transistors in order to increase the scale of integration and high performance of the transistor. Circuitry is configured with two types of transistors differing in the oxide film thickness, i.e., a transistor with a thin gate oxide film and a transistor with a normal gate oxide film (also called thin film transistor and thick film transistor hereinafter) according to the application. Specifically, the entire area of circuitry is reduced by configuring a circuit that is driven at a high operating voltage with a thick film transistor and a circuit driven that is driven at a low operating voltage with a thin film transistor.
FIG. 12 is a schematic diagram of an eDRAM circuit 10000. Referring to FIG. 12, eDRAM circuit 10000 includes DRAM circuitry 10 and ASIC circuitry 11.
In ASIC circuitry 11 in eDRAM circuit 10000 of FIG. 12, a thin film transistor having a thin gate oxide film that is driven at a low operating voltage (approximately 1V to 2V) is employed. In DRAM circuitry 10, two types of transistors driven at a high operating voltage and a low operating voltage, i.e., a thin film transistor and a thick film transistor, are employed according to the application of the control circuit. Specifically, a high voltage of at least the level of a voltage of an H (logical high) level plus a threshold voltage (approximately 3.6V) is applied to the gate of the transistor that forms the memory cell in DRAM circuitry 10 by boosting the word line in a data reading and writing mode. Such a high voltage to the gate of a thin film transistor will cause damage. Therefore, a thick film transistor is used for transistors configuring memory cells. The same applies to other embedded control circuits. A mixture of thick film and thin film transistors are employed in accordance with the application, and an external power supply voltage VDDH of high voltage and an external power supply voltage VDDL of low voltage are employed corresponding to respective transistors.
In circuitry that is related to control of higher accuracy, there is provided a control circuit formed of a thin film transistor that operates upon receiving a predetermined internal voltage generated within the system instead of directly using external power supply voltages VDDH and VDDL in DRAM circuitry 10. A voltage down converter (also called a VDC circuit) is generally employed to generate such an internal voltage. Since this VDC circuit receives a high voltage VDDH for operation, the VDC circuit must be formed of a thick film transistor.
FIG. 13 is a schematic diagram of a conventional VDC circuit 3000 that generates a predetermined internal voltage with respect to a control circuit formed of a thin film transistor.
VDC circuit 3000 receives a reference voltage VREF to generate an internal voltage VDD1 of a level identical to that of reference voltage VREF. VDC circuit 3000 includes a differential amplifier 100, and a P channel MOS transistor P5.
Differential amplifier 100 generates an output voltage CMP according to the voltage difference between reference voltage VREF and internal voltage VDD1. Transistor P5 is connected between external power supply voltage VDDH and a node N14, receiving output voltage CMP of differential amplifier 100 at its gate.
FIG. 14 shows a circuit structure of differential amplifier 100.
Differential amplifier 100 includes P channel MOS transistors 101 and 102, and N channel MOS transistors 103-105.
N channel MOS transistor 105 is connected between a node N3 and ground voltage GND, and receives a bias voltage BIAS at its gate. P channel MOS transistor 102 is disposed between external power supply voltage VDDH and a node N5, and has its gate connected to node N4. N channel MOS transistor 104 is disposed between nodes N5 and N3, and receives reference voltage VREF at its gates. P channel MOS transistor 101 is disposed between external power supply voltage VDDH and node N4, and has its gate connected to node N4. N channel MOS transistor 103 is disposed between node N3 and node N4, and receives an internal voltage VDD1 at its gate. Differential amplifier 100 is supplied with a constant current corresponding to the voltage level of signal BIAS as the operating current. This differential amplifier 100 is of the so-called current mirror configuration, and provides an output voltage CMP according to the voltage difference between internal voltage VDD1 and reference voltage VREF.
FIG. 15 shows a circuit configuration of a reference voltage generation circuit 200 that generates reference voltage VREF.
Reference voltage generation circuit 200 includes a constant current source 224 connected to external power supply voltage VDDH, and supplying a constant current Ids, and N channel MOS transistors 212 and 213.
Each of N channel MOS transistors 212 and 213 provided in series between an output node N7 and ground voltage GND is diode-connected. These diode-connected transistors function as resistance elements.
Reference voltage generation circuit 200 generates reference voltage VREF at output node N7. Reference voltage VREF corresponds to a value of constant current Ids supplied by constant current source 224 multiplied by the combined resistance of the number of stages of the diode-connected transistors. For example, if the combined resistance of transistors 212 and 213 functioning as resistance elements is RS1, the value of reference voltage VREF is set to constant current Idsxc3x97combined resistance RS1.
FIG. 16 is a VREF characteristic diagram of a reference voltage generation circuit. Reference voltage VREF exhibits a substantially constant level even if power supply voltage VDDH rises, as shown in FIG. 16. Since the value of reference voltage VREF can be set based on constant current Ids of constant current source 224, reference voltage generation circuit 200 is not easily affected by a change in the external power supply voltage. An accurate reference voltage VREF can be supplied steadily.
An operation of VDC circuit 3000 in a normal mode will be described here.
When internal voltage VDD1 having the current consumed by the memory cell becomes lower than the voltage level of reference voltage VREF, the level of output voltage CMP, i.e., the gate voltage of P channel MOS transistor P5, is reduced. Accordingly, P channel MOS transistor P5 is rendered conductive, whereby the level of internal voltage VDD1 rises. When internal voltage VDD1 becomes higher than the level of reference voltage VREF, the level of output voltage CMP rises. In response, P channel MOS transistor P5 is rendered non-conductive, whereby the current supply at node N14 is suppressed. Accordingly, internal voltage VDD1 drops to the level of reference voltage VREF.
Thus a predetermined internal voltage VDD1 generated within the system based on an external power supply voltage is generated by a VDC circuit. An accurate internal voltage VDD1 is supplied to a control circuit formed of a thin film transistor.
In order to remove initial failure in advance, accelerated operation aging is applied on the device for a predetermined period of time to screen out any defective products. Burn-in testing is generally employed as one method of screening. The burn-in testing is a method of directly evaluating the dielectric film based on the actual device. By applying stress of high temperature and high electric field, various defective factors such as migration of aluminum wiring are elicited.
In a general burn-in test, a power supply voltage higher than that of normal operation is applied to the transistor forming the control circuit to apply stress of high electric field. Although acceleration of the burn-in testing is increased thereby, there is a possibility of the gate oxide film and the like of the transistor being damaged if the power supply voltage is too high during burn-in testing.
Therefore, an external power supply voltage VDDH# (VDDH#  greater than VDDH) corresponding to external power supply voltage VDDH that is the operating voltage boosted to a predetermined voltage level is supplied to a control circuit formed of a thick film transistor. As to a control circuit formed of a thin film transistor in the above-described eDRAM circuit, an external power supply voltage VDDL# (VDDL# greater than VDDL) corresponding to external power supply voltage VDDL that is the operating voltage boosted to a predetermined voltage level is supplied. Burn-in testing is conducted based on such supplied voltages.
Internal voltage VDD1 supplied to a control circuit related to accurate control is not affected by a change in the external power supply voltage, as mentioned above. Therefore, burn-in testing cannot be conducted for a control circuit formed of a thin film transistor that operates upon receiving internal voltage VDD1, likewise other control circuits.
An approach of supplying an external power supply voltage VDDL# for burn-in testing of a thin film transistor as internal voltage VDD1 in a burn-in test mode can be considered.
Referring to FIG. 13 again, a burn-in voltage supply circuit 3001 is provided for VDC circuit 3000.
Burn-in voltage supply circuit 3001 includes a P channel MOS transistor P6 connected between an external power supply voltage VDDL# for burn-in testing and node N14. P channel MOS transistor P6 receives an input of a burn-in test control signal BI at its gate. Transistor P6 has its substrate electrically coupled to node N14.
An approach of supplying external power supply voltage VDDL# to a control circuit formed of a thin film transistor as internal voltage VDD1 by driving burn-in test control signal BI to an L level (logical low) to turn on P channel MOS transistor P6 can be considered.
According to the structure of supplying a power supply voltage for burn-in testing by means of VDC circuit 3000 and burn-in voltage supply circuit 3001 shown in FIG. 13, both transistors P5 and P6 operate, and are electrically connected to node N14. This structure induces the possibility of the voltage level of the source of transistor P6, for example, being increased prior to the rise of the voltage level of node N14 electrically coupled to the substrate, depending upon the raising order of the external power supply voltages VDDH# and VDDL#. In this case, the so-called latch up occurs at P channel MOS transistor P6. This latch up occurs in the so-called CMOS structure formed of a P channel MOS transistor and an N channel MOS transistor.
FIG. 17 is a sectional view of a CMOS structure formed of a P channel MOS transistor P6 of FIG. 13 and an N channel MOS transistor 105 included in differential amplifier 100 adjacent thereto.
Resistors R1 and R2 and transistors PNP1 and NPN2 are parasitic resistors and parasitic bipolars. Here, the transistor formed at the P well is N channel MOS transistor 105 whereas the transistor formed at the N well is P channel MOS transistor P6.
FIG. 18 is a circuit diagram of an equivalent circuit of the parasitic thyristor formed from the cross sectional view of FIG. 17. This circuit is not a circuit disposed at the substrate, but a parasitic circuit generated by the arrangement of transistors.
Parasitic resistor R1 and parasitic bipolar NPN2 are connected in series between an input node N16 and ground voltage GND, and has its connection node connected to the gate of parasitic bipolar PNP1. Parasitic resistor R2 and parasitic bipolar PNP1 are connected in series between an input node N15 and ground voltage GND, and have their connection node connected to the gate of parasitic bipolar NPN2. Parasitic diode D1 is connected between input nodes N15 and N16 with the forward direction from input node N15 to node N16. Input nodes N15 and N16 receive the inputs of an external power supply voltage VDDL# and an internal voltage VDD1, respectively.
When external power supply voltage VDDL# is pulled up first, forward current flows towards PN parasitic diode D1. The presence of parasitic resistor R1 causes forward bias between the base and emitter of parasitic bipolar transistor PNP1. Amplified current flows between the emitter and the collector. This current will amplify the current between the emitter and collector of parasitic bipolar NPN2. The PNPN thyristor is turned on based on the parasitic bipolar transistor inherent in the CMOS device. Accordingly, excessive current flows between external power supply voltage VDDL-# and GND. Thus, latch up occurs. The occurrence of latch up will not only disrupt the operation of the device, but may also damage the device per se when the heat generated by the excessive current is great.
FIG. 19 shows a circuit structure of a VDC circuit 3100 having burn-in voltage supply circuit 3001 replaced with a burn-in voltage supply circuit 3002. Burn-in voltage supply circuit 3002 includes a P channel MOS transistor P7. Burn-in voltage supply circuit 3002 differs from burn-in voltage supply circuit 3001 in that the substrate voltage of P channel MOS transistor P6 is connected to external power supply voltage VDDL#. The remaining elements are similar.
Latch up likewise occurs in the circuit of a structure modified in the connection of the substrate voltage of the transistor, depending upon the rising order of external power supply voltage VDDL# and external power supply voltage VDDH#.
FIG. 20 is a sectional view of a CMOS structure formed of a P channel MOS transistor P7 and an N channel MOS transistor 105 included in differential amplifier 100 adjacent thereto.
Resistors R1 and R2 and transistors PNP1 and NPN2 are parasitic resistors and parasitic bipolars, respectively. Here, the transistor formed at the P well is N channel MOS transistor 105 whereas the transistor formed at the N well is P channel MOS transistor P7.
FIG. 21 is an equivalent circuit of a parasitic thyristor formed from the sectional structure of FIG. 20.
The structure of FIG. 21 is similar to that described with reference to FIG. 18. Therefore, detailed description thereof will not be repeated here. It is to be noted that an internal voltage VDD1 and an external power supply voltage VDDL# are applied to input nodes N15 and N16, respectively.
According to the present structure, when external power supply voltage VDDH# is pulled up first, i.e. when internal voltage VDD1 is pulled up prior to external power supply voltage VDDL#, forward current will flow to PN parasitic diode D1 due to the low level of the substrate voltage even in the case where the substrate voltage of the P channel MOS transistor is changed to external power supply voltage VDDL#. The presence of parasitic resistor R1 causes bias in the forward direction between the base and emitter of parasitic bipolar PNP1 to conduct a flow of amplified current between the emitter and collector. As a result, that current may cause latch up, i.e., amplify the current between the emitter and collector of parasitic bipolar NPN1. Here, latch up has been described based on a CMOS structure formed of respective transistors P6 and P7 and transistor 105. Similarly, there is a possibility of latch up in a CMOS structure formed of a transistor P5 and transistor 105.
Therefore, the rising order of the external power supply voltage must be taken into consideration in conducting a burn-in test of a control circuit that operates based on internal voltage VDD1. An efficient burn-in test could not be conducted.
An object of the present invention is to provide a semiconductor integrated circuit that can execute burn-in testing efficiently in a control circuit that receives an input of internal voltage VDD1 from a VDC circuit for operation.
According to an aspect of the present invention, a semiconductor integrated circuit includes a first internal circuit, a second internal circuit, and a voltage down converter. In a normal operation mode, the first internal circuit receives a first external power supply voltage to operate. The second internal circuit receives from an internal power supply node an internal voltage of a level lower than the first external power supply voltage to operate. The voltage down converter generates an internal voltage at the internal power supply node. The voltage down converter includes a driver transistor, a burn-in voltage supply unit, and a burn-in control unit. The driver transistor electrically couples the first external power supply voltage with the internal power supply node according to a comparison between a reference voltage indicating a target level of the internal voltage and the internal voltage. The burn-in voltage supply unit electrically couples a second internal power supply voltage of a level lower than the first external power supply voltage and higher than the internal voltage with the internal power supply node in a burn-in test mode. The burn-in control unit forces the driver transistor off in a burn-in test mode. In a burn-in test mode, the first internal circuit receives a third external power supply voltage higher than the first external power supply voltage to operate whereas the second internal circuit receives a second external power supply voltage to operate.
The main advantage of the present invention is that the voltage down converter that supplies an internal voltage based on the first external power supply voltage to the second internal circuit cuts off the supply of the first external power supply voltage by the burn-in control unit in a burn-in test mode. The internal power supply node connected to the second internal circuit receives a second external power supply voltage of a level lower than the first external power supply voltage and higher than the internal voltage from the burn-in voltage supply unit. Accordingly, an effective burn-in test voltage can be supplied to the internal circuit that receives an internal voltage to operate in a burn-in test mode. Also, since the supply of the first external power supply voltage can be cut off, the occurrence of latch up depending upon the rising order of the two power supply voltages electrically connected to the internal power supply node can be obviated. An efficient burn-in test can be conducted with respect to an internal circuit that operates based on an internal voltage.
According to another aspect of the present invention, a semiconductor integrated circuit includes first and second internal circuits, and a voltage down converter. The first internal circuit receives a first external power supply voltage to operate in a normal operation mode. The second internal circuit receives an internal voltage of a level lower than the first external power supply voltage from an internal power supply node. The voltage down converter generates an internal voltage at the internal power supply node. The voltage down converter includes a reference voltage generation circuit, a voltage comparison circuit, a driver transistor, and an external pad. The reference voltage generation circuit generates at an internal node a reference voltage indicating a target level of the internal voltage in a normal operation mode, and suppresses generation of the reference voltage in a burn-in test mode. The voltage comparison circuit compares the voltage at the internal node with the internal voltage. The driver transistor electrically couples the first external power supply voltage with the internal power supply node according to the comparison result of the voltage comparison circuit. In a burn-in test mode, the external pad is coupled to the internal node to receive a second external power supply voltage of a level lower than the first external power supply voltage and higher than the internal voltage. In a burn-test mode, the first internal circuit receives a third external power supply voltage higher in level than the first external power supply voltage to operate.
According to the semiconductor integrated circuit of the present invention, the internal node that receives an input of a reference voltage in a normal mode, and connected to the voltage down converter receives the second external power supply voltage from the external pad in a burn-in test mode. Accordingly, the voltage down converter supplies to the second internal circuit a second external power supply voltage of a level higher than the internal voltage that is applied in a normal operation mode. Therefore, burn-in testing can be conducted efficiently for the second internal circuit that receives the internal voltage to operate in a normal mode.
According to a further aspect of the present invention, a semiconductor integrated circuit includes first and second internal circuits, and a voltage down converter. The first internal circuit receives a first external power supply voltage to operate in a normal operation mode. The second internal circuit receives from an internal power supply node an internal voltage lower in level than the first external power supply voltage to operate. The voltage down converter generates an internal voltage at the internal voltage supply node. The voltage down converter includes first and second reference voltage generation circuits, a voltage comparison circuit, and a driver transistor. The first reference voltage generation circuit generates at an internal node a first reference voltage indicating the target level of the internal voltage in a normal operation mode. The voltage comparison circuit compares the voltage of the internal node with the internal voltage. The driver transistor electrically couples the first external power supply voltage with the internal power supply node according to the comparison result of the voltage comparison circuit. The second reference voltage generation circuit generates at the internal node a second reference voltage lower in level than the external power supply voltage and higher than the first reference voltage in a burn-in test mode. In a burn-in test mode, the second reference voltage generation circuit selectively provides to the voltage comparison circuit one of a plurality of voltages obtained by dividing the external power supply voltage. In a burn-in test mode, the first internal circuit receives the third external power supply voltage higher in level than the first external power supply voltage to operate.
According to the semiconductor integrated circuit of the present invention, the voltage down converter receiving a first reference voltage in a normal operation mode is supplied with a second reference voltage from the second reference voltage generation circuit in a burn-in test mode. The second reference voltage from the second reference voltage generation circuit is adjusted in a burn-in test mode. Accordingly, the voltage down converter can supply a voltage higher in level than the internal voltage applied in a normal operation mode to the second internal circuit. Thus, burn-in testing of the second internal circuit that receives an internal voltage to operate in a normal operation mode can be conducted efficiently.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.